The driver should already handle the transfer of data from the hardware FIFO to a software ring buffer. I suggest you take a look at the existing UART examples on how to use the IDF UART driver API properly.
GitHub - alexforencich/verilog-uart: Verilog UART This is a basic UART to AXI Stream IP core, written in Verilog with MyHDL testbenches. The main code for the core exists in the rtl subdirectory. The uart_rx.v and uart_tx.v files are the actual implementation, uart.v simply instantiates both modules and makes a couple of internal connections. The STM8S buffered UART implementation with support for RS485 \ initilization of buffered UART handler (call this once): UARTISR ( n -- ) 2* ( BR table ) LITERAL + @ UART1_BRR1 ! [ $0C UART1_CR2 ]C! \ enable TX and RX: PINDEBUG: RS485DE: txres rxres; WIPE RAM \\ Example, run e.g. in SWIMCOM: #include UARTISR: UARTISR: txbuf TXLEN 66 FILL: 65 txbuf C! 10 txbuf TXLEN 1- + C! txlen tbp +! start-tx GitHub - kimushu/buffered_uart: UART (RS232C) IP with FIFO UART (RS232C) IP with FIFO buffers for Intel FPGAs - kimushu/buffered_uart MIDI Tutorial - learn.sparkfun.com
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In the initialization function uart_init, the ring buffer should be initialized by calling ring_buffer_init and passing the ring buffer attributes structure with each member assigned the values discussed. If the ring buffer initializes successfully, the UART module can be taken out of reset and the receive interrupt is enabled in IFG2. 26/05/2016 · UART is a great transmission protocol for both hobby and professional projects but, in time-critical systems, UART can be tricky. UART (Universal Asynchronous Reception Transmission), is a popular protocol for microcontrollers to interface between other microcontrollers and computers. The universal asynchronous receiver transmitter module (UART) with first-in first-out (FIFO) buffer MegaCore function performs serial-to- parallel conversion on data characters received from a peripheral device or modem, and parallel-to-serial conversion on data characters received via a bus interface.
Details can be found (including some sample code) in this NIOS II PDF document from Altera. As far as modifying your code to use the interrupt, here is what I would do: Remove uart_checkRecvBuffer(); Change uart_RecvBufferIsr() to something like (sorry no compiler here so can't check syntax/functioning):
\ initilization of buffered UART handler (call this once): UARTISR ( n -- ) 2* ( BR table ) LITERAL + @ UART1_BRR1 ! [ $0C UART1_CR2 ]C! \ enable TX and RX: PINDEBUG: RS485DE: txres rxres; WIPE RAM \\ Example, run e.g. in SWIMCOM: #include UARTISR: UARTISR: txbuf TXLEN 66 FILL: 65 txbuf C! 10 txbuf TXLEN 1- + C! txlen tbp +! start-tx GitHub - kimushu/buffered_uart: UART (RS232C) IP with FIFO